1. Field of the Invention
The present invention relates generally to an arrangement of dynamic random access memory (DRAM) in which capacitances of capacitors can be increased as the memory is miniaturized and a manufacturing method therefor.
2. Description of the Background Art
In recent years, with the remarkable spread of information apparatuses such as computers, there is an increasing demand for semiconductor memory devices. Furthermore, demanded is a semiconductor memory device having a large memory capacity and capable of operating at a high speed. Accordingly, developments have been made in semiconductor memory device technique to achieve high integration and high speed response or high reliability.
Of the semiconductor memory devices, the DRAM capable of inputting and output stored information at random generally comprises a memory cell array which is a storage region for storing a lot of pieces of storage information and peripheral circuits necessary for inputting/outputting the information from/to the outside. FIG. 11 is a block diagram showing an arrangement of a common DRAM. In the drawing, a DRAM 50 comprises a memory cell array 51 for storing data signals of storage information, a row and column address buffer 52 for externally receiving address signals for selecting memory cells constituting a unit storage circuit, a row decoder 53 and a column decoder 54 for decoding the address signals to designate the memory cells, a sense refreshing amplifier 55 for amplifying the signals stored in the designated memory cells and reading the same, a data-in buffer 56 and a data-out buffer 57 for inputting/outputting data and a clock generator 58 for generating clock signals.
The memory cell array 51 occupying a large area of a semiconductor chip has a plurality of memory cells arranged in matrix for storing unit storage information. FIG. 12 is a diagram showing an equivalent circuit of 4-bit memory cells forming the memory cell array 51. Each of the shown memory cells is an one-transistor one-capacitor type memory cell comprising one MOS (Metal Oxide Semiconductor) transistor and one capacitor connected thereto. Since a memory cell of this type has a simple arrangement, it is easy to improve the degree of integration of the memory cell array, and therefore it is widely used in a large capacity DRAM.
In addition, memory cells of the DRAM can be classified into several types depending on capacitor arrangements. FIG. 13 is a sectional view showing an arrangement of a memory cell having a typical stacked type capacitor, which is disclosed in, for example, Japanese Patent Publication No. 60-2784. Referring to FIG. 13, the memory cell comprises one transfer gate transistor and one stacked type capacitor (referred to as a stacked type capacitor hereinafter). The transfer gate transistor comprises a pair of source/drain regions 6, 6 formed in a surface of a silicon substrate 1 and a gate electrode (word line) 4 formed on the surface of the silicon substrate with an insulation layer interposed therebetween. The stacked type capacitor comprises an underlying electrode (storage node) 11 extending from a position above the gate electrode 4 to a position above a field isolation film 2 and a part of which is connected to one of the source/drain regions 6, 6, a dielectric layer 12 formed on a surface of the underlying electrode 11 and an upper electrode (cell plate) 13 formed on a surface of the dielectric layer 12. Furthermore, a bit line 15 is formed on the capacitor with an interlayer insulation layer 20 interposed therebetween, the bit line 15 being connected to the other of source/drain regions 6 of the transfer gate transistor through a bit line contact portion 16. The stacked type capacitor is characterized in that capacitance of a capacitor is ensured by providing the main part of the capacitor extending above the gate electrode and the field isolation film to increase an area where the electrodes of the capacitor are opposed to each other.
Generally, capacitance of the capacitor is proportional to the area where the electrodes are opposed to each other and inversely proportional to a thickness of the dielectric layer. Accordingly, it is desirable to increase the area where the electrodes of the capacitor are opposed to each other from the view point of the increase of capacitor capacitance. Meanwhile, as the DRAM has been highly integrated, the size of a memory cell has been drastically reduced. Accordingly, a capacitor region also tends to have a reduced plane area. However, the charge amount which one-bit memory cell can store should not be reduced from the view point of a stable operation and reliability of the DRAM as a memory device. In order to meet such contradictory requirements, various improvements have been made in an arrangement of capacitor which allow a plane area of the capacitor to be reduced and an area where electrodes are opposed to each other to be increased.
FIG. 14 is a sectional view showing an arrangement of a memory cell comprising a so-called cylindrical stacked type capacitor described in "Symposium on VLSI Tech." p65 (1989). Referring to FIG. 14, a transfer gate transistor comprises a gate electrode (word line) 4c with a periphery covered with an insulation layer 22. Source and drain regions are not shown in the drawing. A word line 4d with a periphery of which covered with the insulation layer 22 is formed on a surface of a shield electrode 40 which is formed on a surface of a silicon substrate 1 with a shield gate insulation film 41 interposed therebetween. An underlying electrode 11 of the capacitor comprises a base portion 11a formed on a surface of the insulation layer 22 covering surfaces of the gate electrode 4c and the word line 4d, and a cylindrical portion 11b vertically and upwardly extending from a surface of the base portion 11a in the form of a cylinder. A dielectric layer and an upper electrode are sequentially deposited on a surface of the lower electrode 11 (not shown). In the cylindrical stacked type capacitor, not only the base portion 11a but also the cylindrical portion 11b can be used as a region for storing electric charges, especially the cylindrical portion 11b enabling the capacitance of the capacitor to be increased without increasing the plane area of the capacitor. A nitride film 42 is left on a part of the surface of the insulation layer 22.
Now, manufacturing steps of the memory cell shown in FIG. 14 will be described with reference to FIGS. 15A through 15F.
First, referring to FIG. 15A, formed on the surface of the silicon substrate 1 into predetermined configurations are the shield gate insulation film 41, the shield electrode 40, the word lines 4a and 4d, the insulation layer 22 and the nitride film 42.
Now, referring to FIG. 15B, a polycrystalline silicon layer is deposited on the surface of the silicon substrate 1, which is patterned into a predetermined configuration. As a result, a base portion 11a of the lower electrode 11 of the capacitor is formed.
Then referring to FIG. 15C, an insulation layer 43 is formed to be thick over the whole surface. Then, an opening portion 44 reaching the base portion 11a of the lower electrode is formed in the insulation layer 43 by etching. A polycrystalline silicon layer 110b is deposited on an internal surface of the opening surface 44 and on a surface of the insulation layer 43.
Referring to FIG. 15D, the polycrystalline silicon layer 110b is selectively etched by the anisotropic etching. As a result, the cylindrical portion 11b is formed which extends vertically and upwardly from the surface of the base portion 11a of the lower electrode 11 of the capacitor, completing the lower electrode 11.
Then, as shown in FIG. 15E, a dielectric layer 12 and an upper electrode 13 are sequentially formed on the surface of the lower electrode 11.
Then, as shown in FIG. 15F, after entirely covering a portion on the silicon substrate 1 with an interlayer insulation layer 20, a contact hole is formed at a predetermined position in which a bit line contact portion 16 is formed. Thereafter, a bit line to be connected to the bit line conductor portion 16 is formed on a surface of the interlayer insulation layer 20 (not shown).
However, as capacity of DRAM is further increased, a plane area of the base portion 11a of the lower electrode 11 is further reduced inevitably in the above-described cylindrical stacked type capacitor. The base portion 11a is largely occupied by a plane surface region reducing in proportion to the reduction of the plane area of the capacitor. In addition, in the cylindrical portion 11b, both of inner and outer surfaces of the cylindrical portion 11b are used as capacitance portions, which occupying an increased area in the entire capacitance regions of the capacitor. Accordingly, it becomes important to make the best use of the cylindrical portion in the reduced plane area of the capacitor.
In addition, the base portion 11a and the cylindrical portion 11b of the lower electrode 11 of the conventional cylindrical stacked type capacitor are formed in different manufacturing steps. Therefore, a plurality of film manufacturing steps and mask patterning steps are required, which makes the manufacturing steps complicated. Furthermore, reliability in insulation of the dielectric layer formed on the surface of the lower electrode 11 is deteriorated in the connection portion between the base portion 11a and the cylindrical portion 11b of the lower electrode 11.
Furthermore, the conventional semiconductor memory device requires a plurality of photolithography steps for manufacturing a cylindrical stacked type capacitor, thereby requiring highly precise registration of a mask. Accordingly, the manufacturing step is made complicated and increases in number.
Description will be made of a conventional DRAM having different stacked type capacitors. A lower electrode of this stacked type capacitor includes a box-shaped standing wall portion.
FIG. 16 is a sectional view showing the arrangement of the memory cell of this DRAM. Referring to FIG. 16, a Si substrate 201 is divided into the respective memory cells by a field oxide film 202.
A MOS transistor for a memory cell comprises a source region 203, a drain region 204 and a gate electrode 205 formed on the surface of the Si substrate 201. Polysilicon, metal, metal silicide and the like are used as a material of the gate electrode 205.
A capacitor cell for use in a memory cell comprises a polysilicon layer 210, a capacitor insulating film 211 having a double or a triple structure including a SiO.sub.2 film and a Si.sub.2 N.sub.2 film and a SiO.sub.2 film, and a polysilicon layer 212 forming a cell plate, all of which films are formed in a CVD.SiO.sub.2 film 213 forming an interlayer insulating film.
Polysilicon layer 210 constituting a storage node has a wall portion standing upwardly at its side and the polysilicon layer 212 forming a cell plate opposite to the inner and the outer surfaces of the wall portion, which increases the surface area of the capacitor, so that a larger capacitance of a capacitor can be obtained in the same area as that of the conventional stacked capacitor cell. In addition, since the capacitor area is larger than that of the stacked capacitor cell of the Embodiment 1, the stacked capacitor cell of the present Embodiment allows a capacitance of the capacitor to become larger than that of the stacked capacitor cell of the Embodiment 1.
Now, a manufacturing method of this stacked capacitor cell will be described.
FIGS. 17A to 17D are diagrams showing the respective manufacturing steps for forming the memory cell shown in FIG. 16.
Referring to FIGS. 17A to 17D and FIG. 16, the manufacturing method of this stacked capacitor cell will be described.
Referring to FIG. 17A, field oxide film 202 which is an element isolation region is formed in the surface of the Si substrate 201 by a LOCOS method and the source region 203 and the drain region 204 are formed through diffusion or ion implantation.
Then, after forming a gate oxide film, polysilicon, high melting point metal, high melting point metal silicide or high melting point metal polycide is deposited on the gate oxide film, which is patterned to form the gate electrode 205.
Then, after depositing the SiO.sub.2 film over the surface by the CVD method, the peripheries of the gate electrode 205 and the other wirings are covered with a CVD.SiO.sub.2 film 206 forming an interlayer insulating film by anisotropic etching.
Referring to Fog, 17B a thin Si.sub.3 N.sub.4 film 207 is deposited over the surface.
Then, after applying a spin on grass (SOG) 208 flat on the entire surface of the Si substrate 201, a resist 209 is applied to the entire surface and then the resist is removed to leave a portion wherein a storage node is formed.
The height of the wall portion of the storage node is determined by a thickness of the SOG 208.
Referring to FIG. 17C, the SOG 208 at the portion wherein a storage node is formed is removed by etching, using the resist 208 (FIG. 10) as a mask.
Then, after exposing the surface of the Si substrate 201 above the drain region 204 to make a contact between the storage node and the drain region 204, the polysilicon layer 210 which is to be a storage node is deposited by a vapor deposition method.
Thereafter, the SOG 208 is removed by etching.
Referring to FIG. 17D, the capacitor insulating film 211 is formed on the surface of the polysilicon layer 210 at the stage where the outer and the inner surfaces of the wall portion standing on the bottom surface of the silicon layer 210 for a storage node are exposed. The capacitor insulating film 211 is formed on the bottom surface, and the outer and inner surfaces of the wall portion of the polysilicon layer 210 for a storage node. A double layer or a triple layer including a thermal SiO.sub.2 film, or a Si.sub.3 N.sub.4 film and a SiO.sub.3 film is used as the capacitor insulating film 211.
Referring to FIG. 16, after the formation of the capacitor insulating film 211, polysilicon layer 212 for a cell plate is deposited and a patterning for the cell plate is carried out.
Then, after depositing the CVD.SiO.sub.2 film 213 forming an interlayer insulating film by the CVD method, a contact is made between the source region 203 and an Al wiring 214.
The stacked capacitor cell according to the present embodiment is completed through the above described steps.
Such a stacked type capacitor allows its capacitors to be increased with the standing wall portion of the storage node 210 provided therein. The Al wiring 214 forming a bit line however contacts the source region 203 on the substrate surface from the upper porion of the capacitor. Therefore, it is necessary to isolate a part of the capacitor located above the gate electrode 205 from the Al wiring 214 by the SiO.sub.2 film 213 having a film thickness needed to maintain the insulation. As a result, a region wherein a capacitor is formed is limited.